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The aim of this paper is to describe the design of a FPGA-based traffic generator able to inject synthetic traffic at gigabit or higher rate. The proposed architecture has been designed to add new features that existing generators do not offer. The generator tries to emulate real network traffic by injecting multiple flows that follow user desired statistical distributions. It offers a generic architecture that can support various protocols. The system also keeps an accurate timing of the injection of each frame. With those features, the proposed system aims to serve as a tool for testing traffic capture systems and other network resources at stress conditions, so research teams can measure and improve the performance of those systems.