The objective of this project is to improve the synchronization between hardware and software computing for devices deployed at the Edge to enable real-time operations. The Internet of Things (IoT) and intelligent systems are becoming heterogeneous computing and networking infrastructures composed of devices at the Edge, Fog, and Cloud. Edge devices provide low-latency operation, while servers in the Cloud and those located in the infrastructure itself provide high computing capabilities and a global perspective of the service. Typically, devices located in the fog and Cloud are computers with abundant hardware and software resources. Therefore, adopting precise synchronization mechanisms is relatively easy. However, IoT devices deployed en masse at the Edge are based on low-cost processing units (CPUs), such as new RISC-V CPUs for embedded systems, which suffer from computational limitations. To address this challenge, this project proposes research into a novel mechanism for sharing a sub-microsecond-precision synchronization layer across hardware, software, and communications computing units. This project will contribute a RISC-V architecture IP CPU compatible with the proposed synchronization mechanism.

Additionally, the aim is to design a fully digital PLL (ADPLL) that supports the above objective and can be used in other generic designs. This CPU will serve as the basis for a new RISC-V-based SoC architecture for edge devices in distributed real-time systems. This contribution will focus on distributed and heterogeneous computing systems. It will enable the optimized execution of real-time tasks with sub-microsecond accuracy, surpassing the state of the art in this field. The feasibility of the proposed contributions will be validated in an experimental design of a SoC semiconductor. This integrated circuit will facilitate experimentation with the innovations obtained. In addition, advancing the TRL of the solution will contribute to the European Union's autonomy in the semiconductor market, given the EU's strategic priority for developing semiconductors based on the RISC-V CPU architecture.