Performing AI inference ubiquitously requires energy-efficient, small footprint and highly reliable processing devices. Heterogeneous processing architectures combining customized CPUs with domain specific coprocessors can provide a good trade-off between computational efficiency and application f lexibility for edge AI deployments while shortening development times compared to full custom application-specific processor designs. Following the impulse for the European sovereignty in the microelectronics field, in this work we propose the use of a RISCV based open-source hardware platform and Free/Libre and/or Open Source (FLOS) Electronic Design Automation (EDA) tools to evaluate the performance of different coprocessor integration options in a System-on-Chip (SoC) prototyped on FPGA. We tested four integration options (XBUS, Stream, CFS and CFU) to obtain precise data that will allow making the correct design decisions for the future development of integrated devices for high-performance AI at the edge.

Overall, the study concludes that CFU is the most suitable coprocessor attachment mode when minimum latency is the priority (typically 8–13 system clock cycles, depending on the accelerator). In contrast, XBUS is the least favorable in terms of throughput (around one-fifth of the data per clock cycle in the evaluated cases). A key takeaway is that the effect of the accelerator’s internal architecture on latency/throughput depends on the selected integration mode, which can be decisive for design choices: CFU benefits low-internal-latency coprocessors, but its advantage narrows as internal latency increases. At the same time, XBUS can be preferable for buffered coprocessors when targeting the highest data throughput.