Cabecera-News
Asset Publisher
RISC-V based Spacewire Node implemented on European Radiation Hardened FPGA Devices
This research presents a SoC implementation of a SpaceWire node, consisting of an open 32-bit RISC-V CPU and an HDL SpaceWire IP core on a European Radiation-Hardened SRAM FPGA (NanoXplore) and a Microchip (Microsemi) FLASH-based FPGA.
First publication date: 21/01/2025
This research presents a SoC implementation of a SpaceWire node, consisting of an open 32-bit RISC-V CPU and an HDL SpaceWire IP core on a European Radiation-Hardened SRAM FPGA (NanoXplore) and a Microchip (Microsemi) FLASH-based FPGA. Both designs were implemented and simulated using the commercial design suites provided by each vendor. Verification of the designs was conducted using two evaluation kits, while the validation of the SoC nodes was performed through conformance tests using SpaceWire commercial testing equipment.