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Research

Research in microelectronic solutions for critical systems is a pillar of the SoC4sensing Chip Chair. The objectives of the research plan are:

  1. Promote lines of research that will advance the design of solutions for microelectronic products, specifically semiconductor devices that can be exploited in the short and medium term.
  2. Explore and develop transversal concepts and capabilities applicable to the Training Plan.

Specifically, the actions promoted by the Chair are focused on the following topics:

  • Prototyping of a semiconductor SoC device with high-availability Ethernet communications and RISC-V CPU on reconfigurable logic of next-generation Intel-Altera SRAM technology

The objective of this project is to obtain a RISC-V CPU-based SoC design for a high-availability Ethernet communications node (HSR/PRP) implemented on the new generation Intel-Altera SRAM technology.

  • Digital Integrated Circuits Design with FOSS (Free and Open Source Software) EDA

The Chip University-Company SoC4sensing Chair offers the university extension course called Design of Digital Integrated Circuits with FOSS EDA to be taught at the School of Engineering of Bilbao. In this course, you will be able to acquire basic skills in the design of digital integrated circuits using these tools, which will lay the foundations for your future career in the emerging field of microelectronics. 

 

  • Synchronization and control of remote quantum sensor systems controlled with RFSoC semiconductor devices

The main objective of this work is to design a network of control systems for distributed quantum systems control instruments using a deterministic TSN network. The instrumentation systems will be based on RFSoC semiconductor devices that integrate all the value-added elements specific to the application in the same integrated circuit: the digital communications hardware, the digital signal processing hardware, the RF, and the application software.

 

  • Embedded CPU architectures for System-on-Chip (SoC):

The proposed actions address the research and experimental development of SoC sub-systems based on RISC-V and ARM microprocessors. The possibility of adapting the RISC-V architecture by integrating custom-developed coprocessors.

 

  • Microelectronic architectures for next-generation industrial communication systems:

The activities driven in this line of work address the research and development of hardware solutions to implement the new communication systems for critical systems integrating OT (real-time) and IT communications. The primary beneficiaries of these contributions are the industrial (Industry 4.0), ENERGY (Smart Grid), and Aerospace sectors.

 

  • Microelectronic architectures for computing applications in systems with advanced Sensorics:

This research line addresses highly specialized research and development activities in a specific sensory application, Dynamic Vision Sensors, which will allow a decline in an experimental Chiplet development integrable in the developed SoC sub-systems. This area's contributions directly apply to industry, automotive, and aerospace.

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RISC-V based Spacewire Node implemented on European Radiation Hardened FPGA Devices

This research presents a SoC implementation of a SpaceWire node, consisting of an open 32-bit RISC-V CPU and an HDL SpaceWire IP core on a European Radiation-Hardened SRAM FPGA (NanoXplore) and a Microchip (Microsemi) FLASH-based FPGA.

First publication date: 21/01/2025

This research presents a SoC implementation of a SpaceWire node, consisting of an open 32-bit RISC-V CPU and an HDL SpaceWire IP core on a European Radiation-Hardened SRAM FPGA (NanoXplore) and a Microchip (Microsemi) FLASH-based FPGA. Both designs were implemented and simulated using the commercial design suites provided by each vendor. Verification of the designs was conducted using two evaluation kits, while the validation of the SoC nodes was performed through conformance tests using SpaceWire commercial testing equipment. 

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