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The proposed Training Plan covers training activities for the following degrees of the Bilbao School of Engineering:
- Bachelor's and Master's Degrees in Telecommunications Engineering
- Master's Degrees in Advanced Electronic Systems
- Doctoral Programs in Electronics and Telecommunications
- Doctoral Programs in Physical Engineering
- Business and Entrepreneurship.
The objectives of the training plan are to strengthen and expand the presence and contribution of highly qualified professionals in the field of telecommunications and advanced electronics, promoting innovation and economic development in the industry.
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Call for Master's and Bachelor's Theses through Aula Chip 2025-2026.
First publication date: 23/07/2025
SoC4sensing's Chip Classroom has launched a range of topics for activities aimed at completing Master's and Bachelor's degree final projects. These activities can be carried out in the Chip Classroom in collaboration with the Chair's partner companies (Ikerlan and SoC-e) and will be supervised by professors from the Bilbao School of Engineering. Each project will receive a financial grant to support the study.
| Design of a Graphene sensor for pollutant gases | The main objective of this work is to develop a graphene sensor for detecting polluting gases, encompassing its design, the fabrication of a prototype, and the creation of a test setup. To achieve this, existing information and designs of graphene-based gas sensors are studied, the sensor is designed using the Klayout tool and the PDK software from Graphenea, the prototype is manufactured, and finally, its functionality is tested in the developed test system. |
| Prototyping a RISC-V based SoC device with quantum secure communications | The project's main objective is to develop a System on Chip (SoC) device with cybersecurity mechanisms resistant to quantum computing attacks for communication links. To achieve this, hardware, software, or hybrid modules are designed and implemented to enable message signing using Dilithium crystals, key exchange using Kyber crystals, and symmetric data encryption using AES-256. These modules are integrated into a prototype SoC controlled by a RISC-V architecture CPU. The work includes a review of the state of the art NIST PQC standard applied to industrial communications, the development of the system architecture, the implementation and integration of the modules, and their verification through simulation and validation in a laboratory environment. |
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Development of a RISC-V-based SoC for Generalised Operational Neural Network (OGNN) |
This project proposes the development of a RISC-V-based SoC with coprocessors specifically designed to provide programming flexibility to OGNNs. The aim is to implement a coprocessor (already designed) capable of efficiently calculating generalised AFs, and to define the new associated instructions to facilitate the programming and execution of OGNNs. A set of non-linear operators alternative to convolution operators will also be defined, and all of this will be integrated into an SoC architecture. |
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Development of a SoC for processing data from a 3D neuromorphic vision sensor (Light Field Dynamic Vision Sensor, LF-DVS) |
The IKERLAN technology centre, in collaboration with its partners in the European Nimble AI project, has developed a DVS equipped with a Light Field microlens layer, which, with additional processing, enables the perception of distances to objects in the image. This project aims to contribute to the design of an SoC for the efficient pre-processing of data generated by an LF-DVS sensor and, in particular, to the development of the SoC's AXI communication infrastructure together with its controller module. |
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Development of processing cores for filtering and discriminating events in neuromorphic vision |
This project aims to develop an event pre-filtering core to eliminate sensor noise, as well as an SNN (Spiking Neural Networks) accelerator core that can be applied to the discrimination of events generated by a DVS (Dynamic Vision Sensor). |
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Sub-Project 1: SoPCtsn5g
Prototyping of a multiprocessor SoC semiconductor device for combining deterministic wired (TSN) and wireless (5G) communication networks based on sub-nanosecond synchronisation (White Rabbit). |
The main objective of this project is to obtain an SoC design that allows the combination of Wired (TSN) and Wireless (5G) Deterministic Communication Networks based on Sub-nanosecond Synchronisation prototyped on System-on-Programmable Chip devices. |
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Sub-Project 2: SoPCwr
Prototyping of a multiprocessor SoC semiconductor device for combining deterministic wired (TSN) and wireless (5G) communication networks based on sub-nanosecond synchronisation (White Rabbit). |
The main objective of this project is to obtain an SoC design that allows the combination of Wired (TSN) and Wireless (5G) Deterministic Communication Networks based on Sub-nanosecond Synchronisation prototyped on System-on-Programmable Chip devices. |
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High Availability Synchronisation Mechanism for Aerospace Communications TSN |
The main objective of this project is to obtain an FTTM (Fault-Tolerant Timing Module) electronic module for new TSN-based embedded communication networks. The operational objectives are: - To obtain an FPGA (SoPC) implementation of the proposed module. - To develop a tapeout (ASIC) of the proposed module. |
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High Availability Synchronisation Mechanism for Aerospace Communications TSN |
The main objective of this project is to obtain an FTTM (Fault-Tolerant Timing Module) electronic module for new TSN-based embedded communication networks. The operational objectives defined in this project are: - To obtain an FPGA (SoPC) implementation of the proposed module. - To develop a tapeout (ASIC) of the proposed module. |
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RISC-V-based SNS-IP core for sub-nanosecond synchronisation |
The main objective of this project is to develop an HDL IP based on White Rabbit technology for sub-nanosecond synchronisation. The operational objectives defined in this project are: - To obtain an HDL IP based on White Rabbit technology for sub-nanosecond synchronisation using a RISC-V CPU as the internal control engine of the IP. - Obtain complete documentation of the IP - Obtain a reference design on a commercial evaluation board based on reconfigurable logic |
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Ethernet-based SoC Extension Mechanism |
Objective: To develop an IP HDL that allows the extension of SoC memory maps and clock systems through a wired Ethernet communication network The operational objectives defined in this project are: - Obtain an HDL IP based on CERN's Etherbone technology that allows the extension of SoC memory maps and clock systems through a wired Ethernet communication network - Obtain complete documentation of the IP - Obtain a reference design on a commercial evaluation board based on reconfigurable logic |
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Evaluation of the ZHAW PTP communications clock synchronisation software stack for use in TSN communications |
The main objective of this project is to evaluate the characteristics of the ZHAW PTP communications clock synchronisation software stack for use in TSN communications using SoCe's TSN IP on an AMD UltraScale+ platform. The operational objectives defined for this project are: - To obtain an embedded system based on the AMD UltraScale + platform and SoCe's TSN IP that integrates the ZHAW PTP stack. - To obtain a comparison between PTP stacks. |
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Digital electronic architecture for SpaceWire communication nodes resilient to SEUs |
The main objective of this project is to develop a digital electronic architecture for SpaceWire communication nodes that is resilient to SEU effects. The operational objectives defined for this project are: - To obtain an electronic architecture described in HDL language for SpaceWire nodes that offers three levels of resilience to SEU effects - To obtain a prototype based on an electronic development board that allows validation of the proposed system - To obtain the criticality of the design generated for the evaluation board developed. |
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Prototyping of an SoC device with bridging functionality between Ethernet and SpaceWire communications |
The main objective of this project is to develop an SoC device with bridging functionality between Ethernet and SpaceWire communications implemented in reconfigurable logic. The operational objectives defined for this project are: - To obtain an electronic architecture described in HDL language to implement SpaceWire nodes with bridging capability between Ethernet and SpaceWire communications - To obtain a prototype based on an electronic development board that allows validation of the proposed system - To obtain a SpaceWire pre-certification report for the proposed system |
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Prototyping of an SoC device with Ethernet communication frame classification capability using Artificial Intelligence techniques |
The main objective of this project is to develop an SoC system capable of classifying Ethernet communication frames using Artificial Intelligence techniques. Operational objectives: - Obtain an electronic architecture for classifying Ethernet communication frames using Artificial Intelligence techniques - Obtain a trained neural network compiled for the AI accelerators of the target semiconductor devices - Obtain a prototype based on an electronic development board that allows the validation of the proposed system |
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Prototyping of an SoC device with integrated RF front-end capable of switching Ethernet packets at 25Gbps for quantum instrumentation applications |
The main objective of this project is to develop a SoC system with 25Gbps Ethernet packet switching capability for quantum instrumentation applications that can be implemented in reconfigurable logic devices with integrated RFSOC-type radio front-ends. |
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Other Electronic Technology projects whose subject matter is aligned with the SoC4Sensing Chair |
The UPV/EHU SoC4sensing Chair will fund activities aimed at developing Master's Theses in the field of digital design, microelectronic design and SoC design for students enrolled in the SIEAV Master's Degree programme. Selected students will have the option of developing their Master's Thesis in the Chair's Chip Classroom under the supervision of professors belonging to the Chair and with access to the equipment and software necessary to carry out their tasks.
Study grants will be awarded on the condition that the projects are ultimately defended.
Requirements:
- Matriculated in official UPV/EHU degree programmes in which the proposed projects can be developed.
- Defence of projects must be completed before 30 June 2026.
- Priority will be given to three study grants for female students applying for this aid.
- The project document and presentation must comply with the obligations relating to the publicity and dissemination of the Catedra Perte project (logos).
Procedure:
- Send an email expressing your interest in applying for this call and indicating your chosen subject(s) to the following address: soc4sensing@ehu.eus
- Include the following TAG in the subject line of the email: [CATEDRA SOC4SENSING] AULA CHIP STUDY GRANTS.
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