Cabecera-Formación
Asset Publisher
The proposed Training Plan covers training activities for the following degrees of the Bilbao School of Engineering:
- Bachelor's and Master's Degrees in Telecommunications Engineering
- Master's Degrees in Advanced Electronic Systems
- Doctoral Programs in Electronics and Telecommunications
- Doctoral Programs in Physical Engineering
- Business and Entrepreneurship.
The objectives of the training plan are to strengthen and expand the presence and contribution of highly qualified professionals in the field of telecommunications and advanced electronics, promoting innovation and economic development in the industry.
Asset Publisher
Call for Master's and Bachelor's Degree Final Projects through Aula Chip 2025
First publication date: 21/01/2025
Through the SoC4sensing Chip Classroom, the offer of topics has been launched for the realization of activities oriented to the realization of Master's and Bachelor's Degree Final Projects. These activities can be carried out in the Aula Chip in collaboration with the collaborating companies of the Chair (Ikerlan and SoC-e) and will be directed by professors of the School of Engineering of Bilbao. Each project will have a financial grant to support the study.
The proposed titles are:
| Prototyping a SoC semiconductor device with high- availability Ethernet communications and a RISC-V CPU in flash-based reconfigurable logic | Complete design (Linux operating system on the RISC-V “ Application Core” processor and HSR/PRP communications IP in the programmable logic part) on a Microchip evaluation kit based on the PolarFire platform SoC |
| Prototyping of a SoC semiconductor device with TSN Ethernet communications and an ARM Cortex-A72 CPU using SRAM technology reconfigurable logic. | Complete design (Linux operating system on the ARM Cortex-A72 processor “ Application Processing Unit ” and TSN communications IP in the programmable logic part) on AMD evaluation kit based on Versal Adaptive platform SoC. |
| Design of an automatable setup for testing IP Cores for semiconductor devices (FPGA, VLSI, etc. ) based on VHDL code based on the Jenkins tool | Obtaining an automatable setup for testing IP Cores for semiconductor devices (FPGA, VLSI, etc. ) based on VHDL code based on the Jenkins tool |
| Design of a digital PID electronic circuit for synchronization and tuning of timers | Development, implementation and validation of a digital electronic circuit that implements a PID algorithm for synchronization and tuning of digital timers. |
| VLSI design of visual event processing pipeline for neuromorphic vision sensor (DVS) | Implement in silicon certain components of a digital pipeline for processing visual events from DVS neuromorphic sensors (https://www.prophesee.ai/event-based-sensor-imx636-sony-prophesee/), which emulate the behavior of retinal photoreceptor cells . The processing pipeline has been developed by Ikerlan within the framework of the European NimbleAI project (https://www.nimbleai.eu/) and the Neuromorphic Initiative . SiliconBurmuin (https://bmh.gaia.es/neuromorphic/), and is currently being prototyped on FPGA. This pipeline includes the following modules: DVS interface with foveation control , event-based filtering, optical flow estimator, event-to -frame conversion , and AXI Stream interface with back- end processor (RISC-V). Note: Several places are offered with the same objectives, as different students may focus on different parts of the pipeline. |
|
Synchronization and control of remote quantum sensor systems controlled by RFSoC semiconductor devices |
Objective: The main objective of this work is to design a network of control systems for instruments controlling distributed quantum systems using a deterministic TSN network. The instrumentation systems will be based on RFSoC semiconductor devices that integrate in the same integrated circuit all the value-added elements specific to the application: digital communications hardware, digital signal processing hardware, RF and application software. |
| Availability Synchronization Mechanism for Aerospace Communications TSN |
The main objective of this project is to obtain an electronic FTTM module ( Fault-Tolerant Timing Module) for new TSN-based embedded communication networks. |
| Design of a digital PID electronic circuit for synchronization and tuning of timers | Development, implementation and validation of a digital electronic circuit that implements a PID algorithm for synchronization and tuning of digital timers. |
| VLSI design of visual event processing pipeline for neuromorphic vision sensor (DVS) | Implement in silicon certain components of a digital pipeline for processing visual events from DVS neuromorphic sensors (https://www.prophesee.ai/event-based-sensor-imx636-sony-prophesee/), which emulate the behavior of retinal photoreceptor cells . The processing pipeline has been developed by Ikerlan within the framework of the European NimbleAI project (https://www.nimbleai.eu/) and the Neuromorphic Initiative . SiliconBurmuin (https://bmh.gaia.es/neuromorphic/), and is currently being prototyped on FPGA. This pipeline includes the following modules: DVS interface with foveation control , event-based filtering, optical flow estimator, event-to -frame conversion , and AXI Stream interface with back- end processor (RISC-V). Note: Several places are offered with the same objectives, as different students may focus on different parts of the pipeline. |
| Availability Synchronization Mechanism for Aerospace Communications TSN | The main objective of this project is to obtain an electronic FTTM module ( Fault-Tolerant Timing Module) for new TSN-based embedded communication networks. Operational objectives: - Obtain an FPGA ( SoPC ) implementation of the proposed module. - Develop a tapeout (ASIC) for the proposed module. |
| Implementation of the Data Processor IP Module for the Dynamic Vision Sensor (DVS) | The objective is the implementation and testing of a digital processing module capable of optimally acquiring and preprocessing the data stream from a neuromorphic vision sensor (DVS). |
| Development of a RISC-V-based SoC for inference of Generalized Operational Artificial Neural Networks ( OGNNs ) | This project proposes the development of a RISC-V-based SoC with coprocessors specifically designed to provide programming flexibility to OGNNs . The aim is to implement an (already designed) coprocessor capable of efficiently computing generalized AFs and defining new associated instructions to facilitate the programming and execution of OGNNs . A set of alternative nonlinear operators to the convolution operators will also be defined , and all of this will be integrated into a SoC architecture. |
| Development of a SoC for processing 3D neuromorphic vision sensor data (Light Field Dynamic) Vision Sensor, LF-DVS) | The IKERLAN technology center, together with its partners in the European Nimble AI project, has developed a DVS equipped with a Light Field microlens layer, which, with some additional processing, allows for the perception of distances to objects in the image. This project aims to contribute to the design of a SoC for the efficient preprocessing of data generated by an LF-DVS sensor and, in particular, to the development of the SoC 's AXI communication infrastructure along with its controller module. |
| Development of processing cores for event filtering and discrimination in neuromorphic vision | This project proposes to develop an event pre-filtering core to eliminate sensor noise as well as an SNN ( Spiking Neural Networks) accelerator core that allows its application to the discrimination of events generated by a DVS ( Dynamic Vision Sensor). |
| - Sub-Project 1: SoPCtsn5g Prototyping of a Multiprocessor SoC semiconductor device for the Combination of Wired (TSN) and Wireless (5G) Deterministic Communication Networks based on Subnanosecond Synchronization (White Rabbit ) |
The main objective of this project is to obtain a SoC design that allows combining Wired (TSN) and Wireless (5G) Deterministic Communication Networks based on Subnanosecond Synchronization. prototyping in System-on-Programmable Chips devices Operational objectives: - Obtain the design of an SoC architecture in which all the communication and synchronization functions planned (TSN, 5G and WR) are considered: SOCall -in- one - Obtain the design of an SoPC architecture in which the communication functions (TSN and 5G) are considered: SoPCtsn5g (Project 1) - Obtain the design of an SoPC architecture in which the synchronization functions (WR) are considered: SoPCwr (Project 2) - Obtain the SoCtsn5g and SoCwr designs applied to an experimental hardware platform |
| - Sub-Project 2: SoPCwr Prototyping of a Multiprocessor SoC semiconductor device for the Combination of Deterministic Wired (TSN) and Wireless (5G) Communication Networks based on Subnanosecond Synchronization (White Rabbit ) |
The main objective of this project is to obtain a SoC design that allows combining Wired (TSN) and Wireless (5G) Deterministic Communication Networks based on Subnanosecond Synchronization. prototyping in System-on-Programmable Chips devices Operational objectives: - Obtain the design of an SoC architecture in which all the communication and synchronization functions planned (TSN, 5G and WR) are considered: SOCall -in- one - Obtain the design of an SoPC architecture in which the communication functions (TSN and 5G) are considered: SoPCtsn5g (Project 1) - Obtain the design of an SoPC architecture in which the synchronization functions (WR) are considered: SoPCwr (Project 2) - Obtain the SoCtsn5g and SoCwr designs applied to an experimental hardware platform |
| Availability Synchronization Mechanism for Aerospace Communications TSN | The main objective of this project is to obtain an electronic FTTM module ( Fault-Tolerant Timing Module) for new TSN-based embedded communication networks. The operational objectives are: - To obtain an FPGA ( SoPC ) implementation of the proposed module. - To develop a tapeout (ASIC) for the proposed module. |
| Core IP for sub-nanosecond synchronization | The main objective of this project is to develop a HDL IP based on White Rabbit technology for Sub-nanosecond Synchronization. The operational objectives defined in this project are: - Obtain an HDL IP based on White Rabbit technology for Sub-nanosecond Synchronization using a RISC-V CPU as the internal control engine of the IP - Obtain a complete documentation of the IP - Obtain a reference design on a commercial evaluation board based on reconfigurable logic |
| Ethernet-based SoC Extension Mechanism |
Objective: Develop an HDL IP that allows the extension of SoCs memory maps and clock system over a wired Ethernet communication network. |
| Evaluation of the ZHAW PTP communications clock synchronization software stack for use in TSN communications | The main objective of this project is to evaluate the characteristics of the ZHAW PTP communications clock synchronization software stack for use in TSN communications using the SoCe TSN IP on an AMD UltraScale + platform. The operational objectives defined for this project are:- Obtain an embedded system based on the AMD UltraScale + platform and the SoCe TSN IP that integrates the Zhaw PTP stack . - Obtain a comparison between PTP stacks. |
| SpaceWire communication nodes resilient to SEU effects | main objective of this project is to develop a digital electronic architecture for SpaceWire communication nodes . resilient to SEUs effects The operational objectives defined for this project are: - Obtain an electronic architecture described in HDL language for SpaceWire nodes that offers 3 levels of resilience against SEUs effects - Obtain a prototype based on an electronic development board that allows the validation of the proposed system - Obtain the criticality of the generated design for the developed evaluation board |
| Prototyping a SoC device with bridging functionality between Ethernet and SpaceWire communications | The main objective of this project is to develop a SoC device with bridging functionality between Ethernet and SpaceWire communications implemented in reconfigurable logic. The operational objectives defined for this project are: - Obtain an electronic architecture described in HDL language to implement SpaceWire nodes with bridging capacity between Ethernet and SpaceWire communications . - Obtain a prototype based on an electronic development board that allows the validation of the proposed system. - Obtain a pre-certification report. SpaceWire of the proposed system |
| Prototyping of a SoC device capable of classifying Ethernet communication frames using Artificial Intelligence techniques | The main objective of this project is to develop a SoC system capable of classifying Ethernet communication frames using Artificial Intelligence techniques. Operational objectives: - Obtain an electronic architecture for the classification of Ethernet communication frames using Artificial Intelligence techniques - Obtain a trained neural network compiled for the AI accelerators of the target semiconductor devices - Obtain a prototype based on an electronic development board that allows the validation of the proposed system |
| Prototyping a SoC device with an integrated RF front-end capable of 25Gbps Ethernet packet switching for quantum instrumentation applications | The main objective of this project is to develop a SoC system with 25Gbps Ethernet packet switching capability for quantum instrumentation applications implementable in reconfigurable logic devices with integrated RFSOC type Front- End Radios. The operational objectives defined for this project are: - Obtain an electronic architecture for 25Gbps Ethernet packet switching - Obtain a SoC architecture (hardware and software) that integrates 25Gbps Ethernet packet switching capability for quantum instrumentation applications implementable in reconfigurable logic devices with integrated RFSoC type Front- End Radios - Obtain a prototype based on an electronic development board that allows the validation of the proposed system - Obtain latency and throughput performance reports for the 25Gbps Ethernet packet switching electronic architecture |
| core RISC-V subsystem for a European ASIC with High Availability Synchronization functionalities | core RISC-V subsystem for a European ASIC with High Availability Synchronization functionalities . The operational objectives defined for this project are: - Obtain an electronic architecture of a 32-bit triple- core RISC-V subsystem with Ethernet network interfaces. - Obtain an SoC architecture (hardware and software) that integrates the PTP synchronization capability in the 32-bit triple- core RISC-V subsystem with Ethernet network interfaces. - Obtain a prototype that implements the front-end of the proposed system. - Obtain a tapeout of the proposed system combined with the FTTM ( Fault-Tolerant) module. Timing Module) (Combined activity with the project: 'High Availability Timing Mechanism for Aerospace Communications TSN). |
| Architecture digital electronics for communication nodes SpaceWire resilient to SEUs effects Chip Design (ASIC) for SpaceWire Communications (2 positions): - Position 1: Front-end design and simulation in VHDL[- Position 2: Back-end ASIC design using Open Source tools] |
Main goal: To obtain an Integrated Circuit Device (ASIC) with SpaceWire networking capabilities. Secondary goals : - To obtain an FPGA version of the design. (Position 1).- To obtain a HDL verification setup ( testbench ) of the design. (Position 1). - To obtain a Tapeout of the design manufacturing in UE fab. (Position 2). - To obtain a validation setup of the design. (Position 2). |
| SoC architecture for packet switching of real-time data traffic | Objective: To contribute a SoC architecture that enables packet switching for real-time traffic using a post-quantum security layer. Sub-objectives: - Study of the art in the field. - Implementation of cryptographic algorithms . - Development and implementation of the SoC architecture . |
| Other Electronic Technology projects whose themes are aligned with the SoC4Sensing Chair | Master's thesis projects carried out in the field of microelectronics of interest to the objectives of the Chip SoC4sensing Chair. |
The UPV/EHU Chip SoC4sensing Chair will fund activities aimed at developing Master's Thesis/FYPs in the fields of digital design, microelectronics design, and SoC design for students of the SIEAV Master's Degree. Selected students will have the option of developing their Master's Thesis in the Chair's Chip Classroom under the supervision of faculty members and with access to the equipment and software necessary to carry out their work.
Study grants will be awarded on the condition that the projects are ultimately defended.
Requirements:
- Enrollment in official UPV/EHU programs in which projects on the proposed topics can be developed.
- Defense of the projects must be completed by June 30, 2026.
- Three study grants will be prioritized for alumnae applying for this grant.
- The project document and presentation must comply with the obligations regarding publicity and dissemination of the Catedra Perte project (logos).
Procedure:
- Send an email indicating your interest in being a beneficiary of this call and the chosen topic(s) to the following address: soc4sensing@ehu.eus
- Include the following TAG in the "Subject" field of the email: TAG: [SOC4SENSING CHAIR] CHIP CLASSROOM STUDY AID GRANTS.
Form
Nested Applications
Asset Publisher