Ongoing improvements in the semiconductor manufacturing processes are the basis of very complex and powerful electronic systems. This movement together with a rapid development in the technology of reconfigurable devices enabled Field Programmable Gate Arrays to grow away from the application as pure glue logic towards becoming an attractive implementation platform for complete electronic applications.

Different attributes of FPGAs, such as a low non-recurring engineering cost, reconfigurability and high data throughput, make these devices an attractive technology for harsh environments. Because of their reconfigurable nature SRAM based FPGAs are especially susceptible to external faults caused by Single Event Upsets. FPGA manufacturers address this issue with specialized FPGA families, but these are typically very expensive and one to two generations behind their latest, most powerful architecture. A consequence of this is a strong interest in techniques, which enable the usage of unprotected FPGAs in critical applications.

This thesis addresses the utilization of Custom Off The Shelf SRAM based FPGAs in environments with an elevated particle ux. The main focus lies on the development and application of suitable test methods for obtaining the exact SEU resilience of a given design. As a first step an external and non-invasive fault injection method is developed addressing the sparsity of fault injectors with low hardware overhead in the currently available state of the art. In a second step a performance improved fault injection method is developed, which includes a universal approach for handling issues related to fault injection using internal configuration ports.

The proposed high performance fault injection platform is both mathematically characterized and evaluated in practice with special focus on different parameters that have a direct influence on the speed of the fault injection and also the accuracy of the obtained results. Finally, the proposed fault injection methods are used to investigate attributes important for fault tolerant applications. Detailed evaluations of the aspects of TMR granularity, SEU resiliences of common application circuits and the impact of adequate validation on the fault injection results are presented.