In the subject Computer Structure (first year of the Informatics Engineering Degree) the students learnt the basic architecture of a Von Neuman computer. Computer Architecture starts from the learnt concepts and summarizes the main techniques used to achieve higher performance in computers.



In the first part we will analyse the cache memory as an element to improve the performance of the access to the information (instructions and data) stored in the memory system. In the second part we will analyse pipelined architectures, studying the hardware as well as the most commonly used compiler techniques to execute programs in an efficient way. Finally, the third part will concentrate on the analysis of the basic characteristics of parallel systems conformed with many computers, particularly we will concentrate on the shared memory systems: performance of parallel systems, synchronisation, task scheduling and parallel programming (OpenMP).



A further step from the acquired knowledge will be given in future year subjects (High Performance Processors and Parallel Computation Systems of the Computer Engineering speciality): on the one hand, advanced techniques to improve the performance of the processors (superescalar processors, multi-core architectures, vector machines and GPUS) and, on the other hand, distributed memory systems for parallel processing. These systems make use of massive parallelism using thousands of processors to diminish the execution time of complex problems.



Thereby the subject is an essential in the knowledge area. It is basic to be able to understand the next subjects of the speciality and it gives a general idea of the topic to students going to other specialities that will be very useful for their career.



Focusing on professional competencies, this subject gives to the students indispensable skills in computer system organization.

The expected learning outcomes are:

1.To identify and analyze the design parameters of cache memories.

2.To analyze the influence of cache memory in the efficiency of the programs' execution.

3.To understand how the pipelined processors work

4.To analyze code optimisations to improve the performance of the processor.

5.To formulate and apply the concepts of parallelism in shared memory multiprocessors.

6.To program simple

parallel aplications facing some problems such as data hazards, synchronisation and load balancing.

1.-CACHE MEMORY.

1.1.-Introduction: memory hierarchy.

1.2.-Main characteristics: size, content, way.

1.3.-Design parameters: mapping, replacement policy, write strategy.

1.4.-Assignments. Optional practical work.



2.-INSTRUCTION LEVEL PARALLELISM (ILP).

2.1.-Motivation: increasing the processors' performance.

2.2.-Design of a pipelined processor: DLX.

2.3.-Data and control hazards.

2.4.-Introduction to multi-cycle and superescalar processors.

2.5.-Compiler techniques for pipelined processors.

2.6.-Assignments.



3.-INTRODUCTION TO PARALLEL COMPUTING SYSTEMS.

3.1.-Introduction. Parallel computers. Flynn's classification. Performance/Efficiency.

3.2.-Shared memory machines: synchronization and load balancing.

3.3.-Programming multiprocessors: OpenMP.

3.4.-Development of a parallel application.



BASIC CONCEPTS OF C PROGRAMMING LANGUAGE

The first two topics of the subject will be taught using two types of classroom activities: master classes and exercise (practical) classes. Both of them will be performed in an active and collaborative way.



The third topic will combine master classes and exercise (practical) classes with laboratory sessions. A practical work, a functional software module and a report about the work carried out in groups will be compulsory in this topic to pass the subject.

• Continuous Assessment System
• Final Assessment System
• Tools and qualification percentages:
  • Percentages and assessed parts are specified in next section (%): 100

The subject has two assessment options: the final assessment and the continuous assessment.



a) Continuous assessment. This is the predetermined option and can only be used in the ordinary call. Active and continuous participation of the students is required: coming to contact lessons and laboratories, assignment and class work delivery, participating in assessment activities, practical works and presentations. When these conditions are not fulfilled the students will be assessed in final assessment.

The continuous assessment will be: written exams (72,5%), assignments (5%) and practical work (22,5%). In both the written exams and the practical work, the minimum mark required is 4 points.

In order to resign to the call, it is enough not to take the exam of the last topic.



b) Final assessment. This will be the option when the student is not in continuous assessment: written exam (80%) and practical work (20%). To pass the subject it is necessary to obtain at least 4 points in both the written exam and the practical work.

In order to resign to the call, it is enough not to take the final exam.





Students who, having fulfilled the conditions for being in the continuous assessment system, decide to opt for the global assessment, must inform via e-mail the lecturers responsible for the subject at the latest after the assessment of the second continuous assessment exam.

The only option for the extraordinary call will be final assessment.

Basic bibliography

1. Hennessy J.L., Patterson D.A.

Computer Architecture: A Quantitative Approach. (6. ed.). Morgan Kaufmann, 2019.

Konputagailuen arkitektura. Hurbilketa kuantitatibo bat. (4 ed.). UPV/EHU, 2008.

Arquitectura de computadores: un enfoque cuantitativo. (1. ed.). McGraw-Hill, 1993.

On-line information (slides, appendices...] in the following address: https://www.elsevier.com/books-and-journals/book-companion/9780128119051



2. Patterson D.A., Hennessy J.L.

Computer Organization and Design: The Hardware/Software Interface. (5. ed.). M. Kaufmann, 2013.

Estructura y diseño de computadores. La interfaz hardware/software. (4. ed.). Reverté, 2011.



3. Ortega J., Anguita M., Prieto A.: Arquitectura de Computadores. Thomson, 2005.



4. Stalling W.

Computer Organization and Architecture. Designing for performance. (8. ed.). Pearson, 2010.

Organización y Arquitectura de Computadores (7. ed.). Pearson - Prentice Hall, 2006.

http://williamstallings.com/COA/COA7e.html



5. Chandra R. et al.: Parallel Programming in OpenMP. Morgan Kaufmann, 2001.



6. Almeida F., Giménez D., Mantas J.M., Vidal A.M.: Introducción a la programación paralela. Paraninfo, 2008.

In-depth bibliography

- Culler D.E., Singh J.P.: Parallel Computer Architecture. A Hardware/Software Approach. M. Kaufmann, 1999.
- Chapman B. et al.: Using OpenMP. Portable shared memory parallel programming. The MIT Press, 2008.
- Pacheco P.S.: An introduction to Parallel Programming. M. Kaufmann, 2011.
- Nemirovsky M., Tullsen D.: Multithreading Architecture. Morgan & Claypool Pub., 2013.
- Hughes C.: Single-Instruction Multiple-Data execution. Morgan & Claypool Pub., 2015.
- Scott M.L.: Shared memory synchronization. Morgan & Claypool Pub., 2013.
- Sorin D.J., Hill M.D., Wood D.A.: A primer on memory consistency and cache coherence. M. & C. Pub., 2011.

Journals

Journals of the area: IEEE Computer, IEEE Micro, ACM...

Web addresses

Web pages of the manufacturers: INTEL, AMD, IBM, etc.
Other web pages: www.top500.org, www.openmp.org...