Several electronic circuits require controlling high-bandwidth data exchange at very high speed: industrial machinery like filling or milling machines, PC peripherals like printers, plotters or recorders, audiovisual equipment, mobile telephones, etc. Today's technology supports the integration on a single chip (SoC, System-on-Chip) of most of the capabilities needed by these complex systems. This Thesis proposes a flexible and scalable architecture for data transfer control in core-based SoC design.

The start point is the specification of a SoC model that is valid for a wide range of applications. The definition and the design of such a generic system have been accomplished on the base of the integration of a set of cores by means of a standard interconnection architecture. The selected topology uses a controller and a bus specifically dedicated to high speed data transfers.

Besides, a simulation platform valid for any application designed by reusing the generic architecture has been developed. This environment allows to verify the functionality of the whole system and to analyze the reliance of system features like bitrate and latency on parameters like the number of simultaneous data transfers, the type of data units, and the type of access to a SDRAM memory. A survey that is very useful to precisely estimate the performance of future applications is also presented.

Finally, all the circuits have been implemented on two FPGAs from two different suppliers in order to achieve these three objectives: to validate the behaviour in real electronic cards, to analyze the dependence of hardware descriptions (performed in VHDL at register transfer level -RTL-) on the technology, and to compare the area and speed results of the different implementations.